Acceleration of FPGA Fault Injection Through Multi-Bit Testing

SRAM-based FPGA devices are an attractive option for data processing on space-based platforms, due to high computational capabilities and a lower power envelope than traditional processing devices. These devices present unique fault-testing challenges as single-event effects can trigger changes in functionality by changing the configuration memory of the device. With each new generation, FPGA configuration memories increase in size and designs increase in complexity, making it very difficult, if not impossible, to perform exhaustive fault-injection testing to verify design reliability. We propose a novel methodology for fault injection in FPGAs using multi-bit testing that can significantly accelerate the process. Traditionally, each bit in configuration memory is tested separately; by testing multiple bits during one test, speedups of more than 10× can be achieved.